| 1. |
- Andersson, Daniel, 1977, et al.
(author)
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Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid
- 2009
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In: 2009 IEEE Workshop on Signal Propagation on Interconnects, SPI '09; Strasbourg; France; 12 May 2009 through 15 May 2009. - 9781424444892
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Conference paper (peer-reviewed)abstract
- Conventional IR drop analysis suggests that on-chip inductive effects can be neglected when estimating supply voltage drops. We present a supply voltage drop analysis for a commercial 32-bit application processor. Our power grid model uses a backbone RL extracted netlist of the processor's power grid, complemented with capacitances from the processor design and a current signature defined by the worst-case switching test vector, located in the power-up sequence of the processor. Our circuit simulations show that on-chip self inductance makes the actual supply voltage drop deviate by more than 55% and 25% from the ∼6% and ∼8% drop, respectively, of nominal supply voltage that a conventional IR power grid model yields.
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| 2. |
- Svensson, Lars, 1960, et al.
(author)
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On-chip power supply noise and its implications on timing
- 2010
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In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. - New York, NY, USA : ACM. ; , s. 389-392
-
Conference paper (peer-reviewed)abstract
- We address two problems of assessing the influence of power- supply variations on timing analysis. We present a method to assign a supply-dependent hold margin; and we describe a method to accurately characterize logic gates for the sen- sitivity of delay on supply-voltage variations. We use a com- mercial microcontroller as a design example.
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| 3. |
- Svensson, Lars, 1960, et al.
(author)
-
Towards Supply-Grid-Based Derating of Timing Margins
- 2009
-
In: 2009 IEEE Workshop on Signal Propagation on Interconnects, SPI '09; Strasbourg; France; 12 May 2009 through 15 May 2009. - 9781424444892
-
Conference paper (peer-reviewed)abstract
- We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spatial map of the supply voltage waveforms. We relate these waveforms to the expected excess logic delays, and estimate the required derating of the critical setup paths.
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